It would be advantageous to implement high speed pulse (data) receivers using complementary symmetry metal oxide silicon field effect transistors (CMOS) in order to be compatible with transceivers such as SONET/ATM transceivers whose core functionality is easily implemented using generic processes such as CMOS.
Further it is advantageous to be able to couple signals into such CMOS implemented transceivers with input signals which are at pseudo emitter coupled logic (PECL) signal levels in a differential mode and which provide output signals into CMOS circuits. In the past, this could only be implemented using an expensive technology such as BiCMOS. It is known that BiCMOS receivers are usually more power hungry than CMOS, since they use conventional current mode logic (CML) architectures. The use of this technology, and the output signal requirements also burden the digital circuits of the receivers with a higher complexity manufacturing process than would be desirable.
A conventional CML approach would have to perform a differential to single ended conversion (unless the designer is willing to use a differential logic scheme throughout the entire digital core), and duty cycle distortion of the output signal presents a problem.